Full Title:Electronic Systems Design
Language of Instruction:English
Module Code:ELEC E7005
Credits: 5
Valid From:Semester 1 - 2014/15 ( September 2014 )
Module Delivered in 2 programme(s)
Module Description:To show how complex digital (and to a lesser extent, mixed-signal) systems can be realised. Specific Aims: 1. To analyse a complex design involving both Digital and Analog parts. 2. To show how a complex design is partitioned. 3. To show how HDL cores may be used. 4. To design and implement a complex mixed signal design
Learning Outcomes:
On successful completion of this module the learner should be able to
  1. Analyse a complex system and Identify major modules within the design and partition appropriately
  2. Develop advanced State Machine design techniques
  3. Compare & contrast various Digital Interface techniques and how they interface to other major cores
  4. Develop designs for testing and readability
  5. Identify sources of electrical noise in a complex system and develop interference suppression techniques.
  6. Develop advanced VHDL skills and apply to the design of various digital cores

Module Content & Assessment

Indicative Content
Design procedures for systems
'Top-Down' vs 'Bottom-Up' design
Advanced VHDL Techniques
Datapaths & RTL design using VHDL
State Machines implementation
Advanced State Machines implementation using VHDL
Serial Interfaces
Design & Implementation of Serial Interfaces (I2C, SPI etc) using VHDL
Clock generation & distribution
Clock distribution techniques
Complex Designs
Complexities of large systems (parallelism & pipelining etc). Systems controlled by one or more state machines
Electrical Noise & Interference suppression
Glitching & Switching concerns
Assessment Breakdown%
Course Work30.00%
End of Module Formal Examination70.00%

Full Time

Course Work
Assessment Type Assessment Description Outcome addressed % of total Marks Out Of Pass Marks Assessment Date Duration
Group Project Practical assignment to implement a complex digital core by applying advanced VHDL techniques 3,4,6 20.00 100 0 n/a 0
Practical/Skills Evaluation Laboratory sessions based around complex systems 1,2,5 10.00 100 0 n/a 0
No Project
No Practical
End of Module Formal Examination
Assessment Type Assessment Description Outcome addressed % of total Marks Out Of Pass Marks Assessment Date Duration
Formal Exam n/a 1,2,3,4,5 70.00 100 0 End-of-Semester 0
Reassessment Requirement
A repeat examination
Reassessment of this module will consist of a repeat examination. It is possible that there will also be a requirement to be reassessed in a coursework element.

DKIT reserves the right to alter the nature and timings of assessment


Module Workload & Resources

Workload: Full Time
Workload Type Workload Description Hours Frequency Average Weekly Learner Workload
Lecture No Description 2.00 Every Week 2.00
Practical No Description 2.00 Every Week 2.00
Directed Reading No Description 2.00 Every Week 2.00
Independent Study No Description 2.00 Every Week 2.00
Total Weekly Learner Workload 8.00
Total Weekly Contact Hours 4.00
This course has no Part Time workload.
Recommended Book Resources
  • Johnson & Graham 1993, High Speed Digital Design, 1e Ed., Prentice Hall [ISBN: 9780133957242]
  • Volnei A. Pedroni 2010, Circuit Design & Simulation with VHDL, 2e Ed., The MIT Press [ISBN: 9780262014335]
  • Frank Vahid 2011, Digital Design with RTL Design, 2e Ed., Wiley [ISBN: 9780470531082]
This module does not have any article/paper resources
Other Resources

Module Delivered in

Programme Code Programme Semester Delivery
DK_EELEG_8 Bachelor of Engineering (Honours) in Electrical and Electronic Engineering 5 Mandatory
DK_EELES_7 Bachelor of Engineering in Electrical and Electronic Systems 5 Group Elective 1