Full Title:Digital Systems Design
Language of Instruction:English
Module Code:ELTR E7006
Credits: 5
Valid From:Semester 1 - 2014/15 ( September 2014 )
Module Delivered in 2 programme(s)
Module Description:Digital hardware is at the core of Electronic Systems today. Digital design using Hardware Description Languages is the norm. The aims of this module are to: 1. Present a systematic method of tackling digital design problems. 2. Enable the Design and Implementation of State Machines. 3. Produce Standard, Synthesizable HDL code. 4. Introduce the Design Flow for Digital Design from specification through verification and implementation using Industry standard CAD packages
Learning Outcomes:
On successful completion of this module the learner should be able to
  1. Identify various Digital Architectures (Synchronous vs Asynchronous, Combinational vs Sequential)
  2. Compare and contrast various programmable logic devices (PLD, CPLD, FPGA).
  3. Design, Verify and Implement Combinational Circuits using VHDL.
  4. Design, Verify and Implement Sequential circuits using VHDL.
  5. Design, Verify and Implement State Machines.
  6. Analyse the Timing and Functional performance of Digital Systems.
  7. Identify & Understand the limitations of VHDL.
  8. Be competent at using a VHDL Industry Standard CAD package.

Module Content & Assessment

Indicative Content
Combinational & Sequential Logic
Design of Counters and Sequencers
Programmable Technology
CPLD and FPGA technology
Introduction to State Machines
Basic State Machines using Karnaugh Mapping
VHDL (Design Language)
VHDL Simulation & synthesis on FPGA and Verification.
VHDL Implementation
VHDL Implementing of simple elements – encoders, decoders, counters etc
Additional VHDL Design
Practice exercises on more complex designs, eg, Mux display, FIFO
Assessment Breakdown%
Course Work40.00%
End of Module Formal Examination60.00%

Full Time

Course Work
Assessment Type Assessment Description Outcome addressed % of total Marks Out Of Pass Marks Assessment Date Duration
Continuous Assessment Laboratory sessions to develop HDL skills 3,4,5,6,8 25.00 100 0 Every Week 0
Class Test Class test to examine digital fundamentals 1,2 7.00 100 0 Week 4 0
Class Test Examine State Machine fundamentals 5 8.00 100 0 Week 8 0
No Project
No Practical
End of Module Formal Examination
Assessment Type Assessment Description Outcome addressed % of total Marks Out Of Pass Marks Assessment Date Duration
Formal Exam Examine core topics covered during semester 1,2,3,4,5,6,7 60.00 100 0 End-of-Semester 0
Reassessment Requirement
A repeat examination
Reassessment of this module will consist of a repeat examination. It is possible that there will also be a requirement to be reassessed in a coursework element.

DKIT reserves the right to alter the nature and timings of assessment


Module Workload & Resources

Workload: Full Time
Workload Type Workload Description Hours Frequency Average Weekly Learner Workload
Lecture No Description 2.00 Every Week 2.00
Practical No Description 3.00 Every Week 3.00
Directed Reading No Description 1.00 Every Week 1.00
Tutorial No Description 1.00 Every Week 1.00
Independent Study No Description 1.00 Every Week 1.00
Total Weekly Learner Workload 8.00
Total Weekly Contact Hours 6.00
This course has no Part Time workload.
Recommended Book Resources
  • Floyd 2009, Digital Fundamentals, 10e Ed., Pearson [ISBN: 978-0-13-8146]
  • Mark Zwolinski 2004, Digital System Design with VHDL, 2e Ed., Prentice Hall [ISBN: 9780130399854]
  • Roth & John 2008, Digital Systems Design using VHDL, 1e Ed., Cengage Learning [ISBN: 978-0-495-244]
This module does not have any article/paper resources
This module does not have any other resources

Module Delivered in

Programme Code Programme Semester Delivery
DK_EELEG_8 Bachelor of Engineering (Honours) in Electrical and Electronic Engineering 4 Mandatory
DK_EELES_7 Bachelor of Engineering in Electrical and Electronic Systems 4 Mandatory